1. Field of the Invention
This invention relates to a hetero junction bipolar transistor (hereinafter abbreviated as HBT) and its manufacturing method.
2 Description of the Related Art
In a prior art system, a spacing between each of the electrodes and a size of each of the electrodes has been made small to realize a high integration and a high operation speed of an HBT. Such an HBT has been made by a process described in Jap.Pat.Laid-Open No.Sho 63-4677. That is, a first semiconductor layer acting as a collector, a second semiconductor layer acting as a base, a third semiconductor layer acting as an emitter, an emitter electrode film in ohmic contact with the third semiconductor layer and an insulation film are piled up in sequence on a substrate of the semiconductor. The insulation film is patterned to a predetermined shape. Thereafter this insulation film is used as a mask, and then the emitter electrode film and the third semiconductor layer are etched to expose the surface of the second semiconductor layer. Then, a first insulation side wall film is formed on the side walls of the emitter electrode layer. The third semiconductor layer is patterned to a predetermined shape. A base electrode film connected to the second semiconductor layer is formed on an entire surface. In addition, the second insulation side wall film is piled up on the side part of the base electrode film, this is used as a mask for etching an exposed portion of the electrode film. A bipolar transistor manufactured by this process shows an advantage that its base electrode is separated from the emitter electrode due to its self-alignment, so that an electrode size or a inter-electrode spacing is made minute thereby realizing a high integration of the elements and at the same time a reduction in its parasitic resistance or parasitic capacitance.
Jap.Pat.Laid-Open No.Sho 62-159464 describes a method for providing connecting portion of the emitter electrode and base electrode to the wiring on the non-active region arranged in the semiconductor substrate.
The prior art described in the aforesaid Jap.Pat.Laid-Open No.Sho 63-4677 has a disadvantage that a junction area has a large area due to no technical consideration on the connection between the emitter electrode and the wiring even though a fine emitter electrode, a fine emitter region and a short distance between the emitter region and the base region could be attained.
The prior art described in the aforesaid Jap.Pat.Laid-Open No.Sho 62-159464 was made such that some contact portions among the emitter electrode, base electrode and wirings are provided on the inactive semiconductor region and showed a problem in that an applied voltage to the emitter-base junction is non-unified due to a resistance of the emitter electrode. In addition, in forming the emitter region, a so-called side etching phenomenon is caused to etch in a lateral direction the semiconductor layer, from which the emitter is formed. The phenomenon presents a problem in forming a fine emitter size.